1. Field of the Invention
The present invention relates to clock schemes in computer systems and memory devices, and in particular to a memory capable of being time-shared by multiple masters using different clocks.
2. Description of Related Art
FIG. 1 illustrates a technique for accessing three random access memories (RAMs): DSRAM 2 (for storing Data), an ISRAM 3 (for storing instructions) and data buffer 7 (for buffering data). DSRAM 2 and ISRAM 3 communicate directly with central processing unit (CPU) 1 via busses 12 and 11, respectively, at the CPU's clock rate frequency. Since RAMs 2 and 3 are directly accessible by the CPU they each have a zero wait access time.
Data buffer 7 is a general purpose data buffer in communication with memory buss 6. Typically memory buss 6 (or System Buss) has a slower clock rate frequency different from that of CPU 1. In addition, data buffer 7 typically has a slower access time than DSRAM 2 and ISRAM 3 because it has lower bandwith requirements. Generally, this is because the buffer 7 supports devices that are slower than the CPU 1.
Memory buss 6 communicates with CPU peripheral buss 4 via a bridge 5. A controller, such as hard disk drive controller 8, controls a disk drive 9. Typically, data flowing to and from a device temporarily is stored in data buffer 7. Thus, a data transfer between the CPU and Disk drive, for instance, traverses a CPU buss 4, a bridge 5, a memory buss 6, and a data buffer 7. A host terminal 10 is in communication with memory buss 6 as well and communicates to the CPU 1 in the same manner.
The size of both the instruction RAM 3 and data buffer 7 are chosen individually. The size of instruction RAM 3 depends upon the maximum program size executed by the CPU, while the size of the data buffer 7 depends upon the data transfer requirements of the application. Once chosen, unless a hardware change is made, the sizes of the instruction RAM 3 and memory 7 are inflexible. A designer therefore must know a priori the size of the instruction set and the transfer requirements for a particular application. Compromises generally are made, making such a selection process an inefficient solution.
Sometimes instruction RAM 3 falls short of the size necessary to store a program (e.g., code). In this case, a portion of data buffer 7 must be allocated to store a portion of the instruction set. Since the CPU does not have direct access to the data buffer 7, it cannot obtain instruction codes stored in a zero access wait time as it could have if it were coupled directly to the memory.
On the other hand, more buffer space may be required to handle larger data transfers. If the data buffer memory 7 is too small, data must be segmented, resulting in lower transfer rates. Accordingly, the memory configuration illustrated in FIG. 1 is inefficient.
There is a need to provide a more flexible memory, and for a configuration which provides a simpler way of allocating memory. There also is a need to provide for controlling such memory allocation in software, and for a memory access technique which is efficient and energy conserving.